期刊
JOURNAL OF MICROELECTROMECHANICAL SYSTEMS
卷 27, 期 4, 页码 686-697出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JMEMS.2018.2843722
关键词
Deep reactive ion etching; DRIE; ultra-high aspect-ratio; through wafer DRIE; DRIE with ramped-parameter recipe; through silicon via (TSV); hole and trench DRIE
类别
资金
- Micro Autonomous Systems & Technology Program of the Army Research Lab [W911NF-08-2-0004]
This paper reports an advanced deep reactive ion etching (DRIE) process for realizing ultra-deep (>500-mu m) and ultra-high aspect-ratio (UHAR) silicon structures (AR > 40 for 1-mm through-trench etch, AR approximate to 80 for 500-mu m through-trench etch, and AR > 20 for 500-mu m through-hole etch), with straight sidewalls across a wide range of feature sizes. The challenges of making such structures are overcome by continuously ramping critical parameters of the Bosch DRIE process throughout the process, including the 380-kHz bias power during etch step, the etch/passivation step duration, and the chamber pressure. The masking material capable of enduring the long DRIE process is also discussed; 10-mu m and 25-mu m wide trenches are etched to a depth of >750-mu m and >1000-mu m, respectively, in 1-mm-thick silicon wafers with straight sidewall profiles and flat trench bottoms. Deeper trenches are expected to be etched beyond a 1-mm thick wafer with thicker and/or higher selectivity masking materials. We have also demonstrated etching of circular holes of diameters as small as 25-mu m to a depth of >500-mu m, and potentially with 10-15 mu m diameter holes. This advanced DRIE process offers opportunities for applications ranging from through-silicon via in 3-D CMOS integration to emerging micro- and mesa-scale microelectromechanical system applications that demand ultra-deep and UHAR DRIE.
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