Performance Evaluation of Digital Comparator Using Different Logic Styles

In the present scenario, low power, speed, and size play a significant role specifically in the field of digital VLSI circuits. The major goal of this paper is to design and implement a digital comparator using different logic techniques to compare power consumption, propagation delay, and transistor count. The results of this paper are simulated on the EDA tanner tool realized in 45-nanometer technology at 0.7 v supply voltage.