期刊
IET CIRCUITS DEVICES & SYSTEMS
卷 12, 期 4, 页码 505-513出版社
INST ENGINEERING TECHNOLOGY-IET
DOI: 10.1049/iet-cds.2017.0412
关键词
analogue-digital conversion; calibration; low-power electronics; biomedical equipment; CMOS logic circuits; SAR ADC; low-power successive approximation register analogue-to-digital converter; medical instrument applications; foreground digital-domain calibration method; mismatch error correction; capacitive digital-to-analogue converter; split-CDAC array architecture; V-cm-free technique; floating CDAC scheme; power hungry V-cm generator; modified direct-switching SAR logic; 1P6M CMOS technology; signal-to-noise and distortion ratio; word length 16 bit; size 0; 18 mum; noise figure 86; 16 dB
资金
- Chinese National Natural Science Foundation [61376038, 61774103, 61404084]
This study presents a low-power 16-bit 1-MS/s successive approximation register analogue-to-digital converter (SAR ADC) for medical instrument applications. A foreground digital-domain calibration method simultaneously correcting mismatch errors in capacitive digital-to-analogue converter (CDAC) and segment error' of split-CDAC array is proposed. The split-CDAC architecture combines a V-cm-free technique in a floating CDAC scheme. The V-cm-free technique avoids a power hungry V-cm generator, and the floating CDAC scheme allows the conversion of a high-voltage input signal with low supply voltage and without a significant attenuation of the input signal. Moreover, a modified direct-switching SAR logic is adopted to improve the conversion speed. The prototype was fabricated in a 0.18 mu m 1P6M Complementary Metal Oxide Semiconductor (CMOS) technology, and achieves 86.16dB signal-to-noise and distortion ratio and an Figure of Merit (FOM) of 0.41pJ/conversion-step.
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