期刊
IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS
卷 14, 期 2, 页码 748-758出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TII.2017.2754641
关键词
Cycle time (CT); data driven; long-short-term memory (LSTM); recurrent neural network (RNN); re-entrant manufacturing; semiconductor wafer manufacturing system
类别
资金
- National Science Foundation of China [51435009]
Forecasting short-term cycle time (CT) ofwafer lots is crucial for production planning and control in the wafer manufacturing. A novel recurrent neural network called bilateral long short-term memory (bilateral LSTM) is proposed to model a short-term cycle time forecasting (CTF) of each re-entrant period of a wafer lot. First, a two-dimensional (2-D) architecture is designed to transmit the wafer and layer correlations by using wafer and layer connections. Subsequently, aiming to store various error signals caused by the diverse CT data, a multiply memory structure is presented to extend the capacity of constant error carousel (CEC) in the LSTM model. The experiment results indicate that the proposed model outperforms conventional models in the accuracy and stability for the short-term CTF. Further comparative experiments reveal that the 2-D architecture can enhance the prediction accuracy and the multi-CEC structure can improve the forecasting stability for the short-term CTF of wafer lots.
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