期刊
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
卷 65, 期 5, 页码 562-566出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCSII.2018.2820181
关键词
Time-to-digital conversion; multi-hit; time resolution; double-hit-resolution; delay-line; timing
资金
- German Research Foundation through the HAEC Project [A01, 1120807]
- Fast-Spot Project within the Bundesministerium fur Bildung und Forschung Cluster FAST
Several new approaches for multi-hit delay-linebased time-to-digital converters (TDCs) are discussed and an input-sampled TDC architecture is realized in 45-nm SOI CMOS. The TDC is characterized by applying a pseudo-randombit-sequence as an input signal, which consists of multiple time-events/hits. Each low or high transition inside the binary input represents a time-event to be recorded. As the time-event carrying input travels through the delay-line, it generates its delayed phases, which are then sampled by a reference clock with period equal to the delay of the delay-line. The resulting sampled digital word contains a snapshot of all the time-events occurring within one clock period. The TDC achieves a time-resolution of 25 ps and the continuous sampling of the delay-line allows this unique architecture to achieve ideally unlimited dynamic-range. The prototype circuit dissipates 16 mW of power, occupies silicon area of 0.36 mm(2), and is capable of detecting two consecutive time-events/transitions at a distance of 250 ps, which is the best double-hit-resolution reported in literature for any TDC.
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