期刊
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
卷 65, 期 3, 页码 881-890出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCSI.2017.2771364
关键词
High-resolution SAR ADC; residue oversampling; capacitor mismatch; DEM; calibration-free
资金
- Ministry of Science and Technology, Taiwan [MOST 105-2221-E-006-240-MY3]
This paper presents a new circuit technique named residue oversampling, which is suitable for high-resolution analog-to-digital converters (ADCs). By adopting this technique and simplifying the dynamic element matching, the impacts of capacitor mismatch and noise upon the successive-approximation register ADCs are reduced significantly without calibrations. The proof-of-concept prototype was fabricated in TSMC 40-nm CMOS technology. At 40-MS/s and 10-MS/s sampling rates, the measured peak signal-to-noise and distortion ratios are 66.84 and 69.78 dB, respectively.
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