期刊
IEEE PHOTONICS TECHNOLOGY LETTERS
卷 30, 期 7, 页码 591-594出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LPT.2018.2791631
关键词
Silicon waveguide patterning; line edge roughness (LER); smoothing treatments; optical losses; photonic integrated circuits (PICs)
资金
- French National program Programme d'investissment d'avenir, IRT Nanoelec [ANR-10-AIRT-05]
- French RENATECH network
We report the successful fabrication of low-loss submicrometric silicon-on-insulator strip waveguides for on-chip links. Postlithography treatment and postetching hydrogen annealing have been used to smoothen the waveguide sidewalls, as roughness is the major source of transmission losses. An extremely low silicon line-edge roughness of 0.75 nm is obtained with the optimized process flow. As a result, record-low optical losses of less than 0.5 dB/cm are measured at 1310 nm for strip waveguide dimensions exceeding 500 nm. They range from 1.2 to 0.8 dB/cm for 300-400-nm-wide waveguides. Those results are to our knowledge the best ever published for a 1310-nm wavelength. These results are compared to modeling based on Payne and Lacey equations.
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