Low-power and high-throughput 128-point feedforward FFT processor

Fast Fourier Transform (FFT)/Inverse Fast Fourier Transform (IFFT) are the key computation block in Orthogonal Frequency Division Multiplexing (OFDM) system. They dominate most of the areas and power dissipation in implementation therefore efficient low-power and high-throughput implementation of FFT processor is essential for successful deployment of OFDM based system. High-throughput and Low-power 128-point FFT Processor is designed using Radix-2(5) algorithm to reduce computation complexity and the feedforward pipeline architecture [called Multipath Delay Commutator (MDC)] with four data path for providing higher throughput. This architecture is more hardware-efficient than Multipath parallel feedback (MDF) design, which makes them attractive for the computation of FFT in most demanding applications. The proposed FFT processor uses improved Digit slice multiplier for complex multiplication. This proposed FFT processor is designed using Verilog and implemented using 180 nm CMOS Technology with supply voltage of 1.8v. The result shows significant reduction in power consumption in comparison with existing design and increasing throughput with area trade off.