期刊
CRYSTALS
卷 7, 期 6, 页码 -出版社
MDPI
DOI: 10.3390/cryst7060162
关键词
graphene; SiC; interface; buffer layer; barrier height; carrier transport
资金
- European Union's Horizon research and innovation program [696656]
- Vetenskapsradet (VR) [621-2014-5805]
- Stiftelsen for strategisk forskning [SSF GMT14-0077, SSF RMA15-0024]
- Angpanneforeningens Forskningsstiftelse [16-541]
- Swedish Research Council (VR) Marie Sklodowska Curie International Career Grant [2015-00679]
- AForsk [14-517]
- Wallenberg foundation
- Swedish Research Council [2015-00679] Funding Source: Swedish Research Council
In spite of the great expectations for epitaxial graphene (EG) on silicon carbide (SiC) to be used as a next-generation high-performance component in high-power nano- and micro-electronics, there are still many technological challenges and fundamental problems that hinder the full potential of EG/SiC structures and that must be overcome. Among the existing problems, the quality of the graphene/SiC interface is one of the most critical factors that determines the electroactive behavior of this heterostructure. This paper reviews the relevant studies on the carrier transport through the graphene/SiC, discusses qualitatively the possibility of controllable tuning the potential barrier height at the heterointerface and analyses how the buffer layer formation affects the electronic properties of the combined EG/SiC system. The correlation between the sp(2)/sp(3) hybridization ratio at the interface and the barrier height is discussed. We expect that the barrier height modulation will allow realizing a monolithic electronic platform comprising different graphene interfaces including ohmic contact, Schottky contact, gate dielectric, the electrically-active counterpart in p-n junctions and quantum wells.
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