Analysis and feasibility of an evaporative cooling system with diffusion-based sessile droplet evaporation for cooling microprocessors

In this study, a feasibility analysis is undertaken to assess the capability of an evaporative cooling system using diffusion-based evaporation of sessile water droplets to provide sufficient cooling of microprocessors within the space requirements of the current heat sinks. The study investigates the cooling requirements for the Intel Xenon Processor and the Intel Core i7-900 Processor. An analytical model is developed to determine the capacity of a single layer of water droplets to provide sufficient cooling and calculates the size of the droplets required to meet the cooling needs. It is found that a single layer can provide sufficient cooling for the Xenon Processor with 21,316 droplets having a radius of 0.25 mm and the Core i7-900 Processor with 27,556 droplets having a radius of 0.25 mm. A numerical model is developed to analyze a tiered system that fits within the space restrictions corresponding to the current heat sinks, but can provide the required cooling needs with larger droplets and fewer of them. To decrease the complexity of manufacturing the evaporative cooling system, the numerical model simulated cases to find both (i) the minimum number of posts required to connect each of the tiers and (ii) the minimum number of tiers required to provide sufficient cooling for the microprocessors. The results of the numerical modelling work found that a minimum of 60 posts connecting each of the tiers were required to cool the Xenon Processor and 52 posts for the Core i7-900 Processor. It was also found that a minimum of 3 tiers was required for the Xenon Processor, with a total of 867 droplets having a radius of 2 mm, and 5 tiers required for the Core i7-900 Processor, with a total of 1620 droplets having a radius of 2 mm. The results of the work demonstrate that evaporative cooling systems with diffusion-based evaporation of sessile droplets can provide sufficient cooling for the selected microprocessors, with a number of feasible configurations. (C) 2017 Elsevier Ltd. All rights reserved.