Ultra-low-Voltage Integrable Electronic Realization of Integer- and Fractional-Order Liao's Chaotic Delayed Neuron Model

The neurons are proven to show chaotic dynamical behavior, and due to this behavior, they find applications in several fields. Recently, the chaotic behavior of the neuron model using non-monotonous Liao's activation function was described and its design using op-amp was presented. The presented design is a high-voltage one and is not integrable, as both passive resistors and inductors have been employed. Besides, most of the components are of floating type, which are difficult to design on an integrated chip. In addition, only integer-order design has been considered. In this paper, an ultra-low-voltage sinh-domain implementation of the neuron model has been introduced. Moreover, for the first time, the fractional-order implementation of the model has also been presented. The design offers the advantages of: (a) low-voltage implementation, (b) integrable design, (c) resistor and inductor less design, (d) using only grounded components, and (e) low-power design due to the inherent class AB nature of sinh-domain technique. The proper functioning of the model has been verified through different cases where the time constant of the integrator, delay and fractional order have been varied. The behavior of the neuron models is evaluated through HSPICE simulator using the metal oxide semiconductor transistor (MOSFET) models provided by Taiwan Semiconductor Manufacturing Company Limited (TSMC) 130 nm complementary metal oxide (CMOS) process.