High-gain monolithic 3D CMOS inverter using layered semiconductors

We experimentally demonstrate a monolithic 3D integrated complementary metal oxide semiconductor (CMOS) inverter using layered transition metal dichalcogenide semiconductor Nchannel (NMOS) and P-channel (PMOS) MOSFETs, which are sequentially integrated on two levels. The two devices share a common gate. Molybdenum disulphide and tungsten diselenide are used as channel materials for NMOS and PMOS, respectively, with an ON-to-OFF current ratio (ION/IOFF) greater than 10 6 and electron and hole mobilities of 37 and 236 cm 2 /Vs, respectively. The voltage gain of the monolithic 3D inverter is about 45V/V at a supply voltage of 1.5V and a gate length of 1 lm. This is the highest reported gain at the smallest gate length and the lowest supply voltage for any 3D integrated CMOS inverter using any layered semiconductor. Published by AIP Publishing.