期刊
2017 47TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC)
卷 -, 期 -, 页码 252-255出版社
IEEE
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资金
- French Public Authorities through NANO program
- Qualcomm
- French Public Authorities through EQUIPEX FDSOI11
- French Public Authorities through ST-LETI Alliance program
For the first time the thermal stability of a new fluorine-free (F-free) W barrier coupled with W interconnections enabling 22% line 1 resistance improvement is evaluated in view of 3D VLSI integration. Integrated with ULK, no resistance nor lateral capacitance degradation is observed up to 550 degrees C 5h while preserving good reliability. For additional thermal stability a TEOS/W stability is demonstrated up to 600 degrees C 2h. Both types of interconnection stacks have been successfully integrated on devices with 28nm design rules and show similar performance for MOSFETs and Ring Oscillators (RO) as compared to the ULK/Cu stack. Finally, iBEOL guidelines are given at the end in view of 3D sequential integration.
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