期刊
SOLID-STATE ELECTRONICS
卷 130, 期 -, 页码 9-14出版社
PERGAMON-ELSEVIER SCIENCE LTD
DOI: 10.1016/j.sse.2016.12.008
关键词
3D transistors; Nanowire; Gate-all-around; MOS scaling
资金
- French RENATECH network (French national nanofabrication platform)
A vertical MOS architecture implemented on Si nanowire (NW) array with a scaled Gate-All-Around (14 nm) and symmetrical diffusive S/D contacts is presented with noteworthy demonstrations in both processing (layer engineering at nanoscale), and in electrical properties (high electrostatic control, low defect level, multi-Vt platform). Furthermore, the versatility and reliability of this technology is evidenced with a CMOS inverter, providing bright perspectives for ultimate scaling. (C) 2017 Elsevier Ltd. All rights reserved.
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