Frequency Synthesis Based on A Novel Differential Locking Mechanism

In this frequency synthesis architecture, instead of a reference clock, two frequencies derived from the VCO output are fed into the PFD, one increasing with VCO frequency and one decreasing. Existing Alias-Locked Loops (ALLs) use digital samplers in the feedback path to achieve wide frequency range of control for high speed frequency synthesis, with the cost of one additional reference clock compared to a PLL. In this paper, we propose the differential alias-locked loop (D-ALL) circuit architecture which uses a single reference clock input. Instead of comparing the feedback signal with a reference clock, two feedback signals are compared with each other in a D-ALL. A D-ALL has the advantage of wide frequency range of operation and low silicon area cost compared to a traditional high-frequency PLL. Spectre simulation has verified that the proposed design achieves lock at an example target frequency of 9.7 GHz.