3.8 Proceedings Paper

An Optimized Hardware Design for high speed 2D-DCT processor based on modified Loeffler architecture

出版社

IEEE
DOI: 10.1109/iraniancee.2019.8786608

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2D-DCT transform; high speed architecture; 8*8 block; threshold; image compression; video compression; VHDL

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Discrete Cosine Transform (DCT) has an important role in image compression. This paper presents a fast 2D-DCT architecture for hardware efficient embedded systems and power limited applications such as Internet of Things (IoT). The proposed design both from a structure point of view and operation reduction point of view has two headed approaches toward the problem of image and video compression. It includes a modified high speed architecture using an extra operational reducing technique. Reduction of operations occurs in two stages while computing 8 point DCT transform of the blocks. Defining the appropriate threshold for comparing DCT domain of two rows of an 8*8 block. Approximating DCT operations column-wise is the additional approach of the paper. The architecture is implemented on Xilinx Vivado 2018.2 with VHDL language on Artix-7 FPGA. 207 MHz clock frequency has achieved.

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