期刊
IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY
卷 7, 期 1, 页码 1225-1231出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JEDS.2019.2936180
关键词
3D IC; through-silicon vias; charge pumping method; interface trap
资金
- VLSI Design and Education Center, the University of Tokyo
- Cadence Design Systems
- Micro/Nano-Machining Research and Education Center at Tohoku University
Mixed-signal 3D-ICs have a stacked structure of digital and analog circuit chips. In this study, the effect of noise propagation from a digital circuit on an analog circuit was evaluated using an actual mixed-signal 3D-IC. The noise propagation via through-silicon vias (TSVs) was measured, with a ring-oscillator as a noise source. For a comprehensive investigation, TSV-liner interface states were evaluated along the depth direction using unique multiwell-structured TSVs and a charge-pumping method. It was considered that the interface traps and nonconformal thickness of the TSV liner increased the noise propagation among stacked chips.
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