期刊
IEEE ACCESS
卷 7, 期 -, 页码 172774-172782出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/ACCESS.2019.2956179
关键词
Computation reuse; electrocardiogram (ECG) processor; input similarity; neural networks
资金
- National Natural Science Foundation of China [61801425]
This paper presents a neural network based processor with improved computation efficiency, which aims at multiclass heartbeat recognition in wearable devices. A lightweight classification algorithm that integrates both bi-directional long short-term memory (BLSTM) and convolutional neural networks (CNN) is proposed to deliver high accuracy with minimal network scale. To reduce energy consumption of the classification algorithm, the similarity between consecutive heartbeats is exploited to achieve a high degree of computation reuse in hardware architecture. In addition, neural network compression techniques are adopted in the procedure of inference to save hardware resources. Synthesized in the SMIC 40LL CMOS process, the prototype design has a total area of 1.40 mm(2) with 186.2 kB of static random-access memory (SRAM) capacity. Based on the simulation, this processor achieves an average energy efficiency of 3.52 GOPS/mW under 1.1 V supply at 100 MHz frequency. Compared with the design without computation reuse, the proposed processor provides a speedup by 2.58x and an energy dissipation reduction by 61.27% per classification. This work is a valuable exploration of neural network based design for long-term arrhythmia monitoring in daily life.
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