期刊
2019 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI 2019)
卷 -, 期 -, 页码 170-175出版社
IEEE COMPUTER SOC
DOI: 10.1109/ISVLSI.2019.00039
关键词
In-sensor Processing; Reconfigurability; Attention Module; Image Sensor; ASIC
资金
- National Science Foundation (NSF) [1618606]
- Division Of Computer and Network Systems
- Direct For Computer & Info Scie & Enginr [1618606] Funding Source: National Science Foundation
This paper presents a hardware architecture to extract features from an image using the concepts of bio-inspired computing and a method of converting sequential image processing to parallel computational processing units that can execute on the sensor. These computational units are oriented on vertically integrated hierarchical planes and enabled with a region based Attention Module which separates the Regions of Interest (ROIs) from the image. In each layer, the computational units work in parallel and introduce massive parallelism at the pixel level. At the same time, the design saves dynamic power by dynamically enabling and disabling the computational units which ensure high-performance and high-throughput. Moreover, the units are made reconfigurable to support a wide range of machine vision applications by forming a basic structure that is common to all operations and reconfigurable parts for a specific application. Our simulation result shows the design achieves 4.852x power savings on ROIs while processing at 465 Kfps with 800 MHz clock frequency.
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