期刊
2019 IEEE 26TH SYMPOSIUM ON COMPUTER ARITHMETIC (ARITH)
卷 -, 期 -, 页码 92-95出版社
IEEE COMPUTER SOC
DOI: 10.1109/ARITH.2019.00023
关键词
reduced precision computation; floating point; machine learning; deep learning
The resilience of Deep Learning (DL) training and inference workloads to low-precision computations, coupled with the demand for power- and area-efficient hardware accelerators for these workloads, has led to the emergence of 16-bit floating point formats as the precision of choice for DL hardware accelerators. This paper describes our optimized 16-bit format that has 6 exponent bits and 9 fraction bits, derived from a study of the range of values encountered in DL applications. We demonstrate that our format preserves the accuracy of DL networks, and we compare its ease-of-use for DL against IEEE-754 half-precision (5 exponent bits and 10 fraction bits) and bfloat16 (8 exponent bits and 7 fraction bits). Further, our format eliminated sub-normals and simplifies rounding modes and handling of corner cases. This streamlines floating-point unit logic and enables realization of a compact power-efficient computation engine.
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