FPGA Hardware Co-Simulation of Image Encryption Using Stream Cipher Based on Chaotic Maps

In this paper, new model of image encryption system using stream cipher based on fixed point chaotic maps are designed using Xilinx System Generator (XSG) in efficient way. Two Pseudo Random Bit Generators (PRBGs) depends on chaotic maps are proposed that are Fixed Point XOR Chaotic Map-PRBG (FPXORCM-PRBG) and Fixed Point Cascade Chaotic Map-PRBG (FPCCM-PRBG). The randomness tests in the National Institute of Standards and Technology (NIST) are used to test the randomness measures of the proposed PRBGs. The security analysis, like histogram, correlation coefficient, information entropy, differential attack (NPCR and UACI) are used to analyze the proposed system. Also, FPGA Hardware Co-Simulation over Xilinx SP605 XC6SLX45T provided to test the reality of image encryption system. The results show that FPXORCM-PRBG and FPCCM-PRBG are suitable for image encryption based on stream cipher and outperforms some encryption algorithms.