期刊
出版社
IEEE
DOI: 10.1109/icaccs48705.2020.9074407
关键词
Switching activity; stuck-at fault; transition fault; LFSR; AOI; NAND; NOR implementation; dynamic power
Low power technology emerges with increasing transistor count in a miniaturized silicon chip. Power optimization in technology, circuit, layout, logic, architecture and algorithmic levels should be mandatory. Hierarchical level of testing in digital devices to meet the customer requirements will increase device power consumption. Increased test power is the result of built in testing structures embedded in the devices. Test vectors applied during testing suffers from increased transition of vectors from one stable state to another, which causes too much of power loss in digital devices. This paper is proposed to measure the switching activity and dynamic power consumption of the circuits implemented in AOI, NAND and NOR format. Peak and average switching activity and peak dynamic power consumption for the circuits at different implementation during normal and test mode are estimated. The resultant values are compared against each implementation and the best with minimum switching activity and dynamic power is preferred to design a low power circuit.
作者
我是这篇论文的作者
点击您的名字以认领此论文并将其添加到您的个人资料中。
推荐
暂无数据