4.4 Article

Single-phase ac-dc-ac topology for grid overvoltage and voltage harmonic mitigation

期刊

IET POWER ELECTRONICS
卷 10, 期 12, 页码 1626-1637

出版社

INST ENGINEERING TECHNOLOGY-IET
DOI: 10.1049/iet-pel.2016.0934

关键词

power supply quality; AC-DC power convertors; DC-AC power convertors; power factor; uninterruptible power supplies; single-phase ac-dc-ac topology; grid overvoltage mitigation; voltage harmonic mitigation; floating capacitor H-bridge converter; three-leg topology; regulated load voltage; fixed amplitude; fixed frequency; low harmonic content; unitary power factor; unified power quality compensator; uninterrupted power supply; UPS; asymmetrical dc-link voltages; multilevel input voltages; cascaded H-bridge; voltage levels; harmonic distortion; switching stress; power losses; validation purposes

资金

  1. National Council of Technological and Scientific Development (CNPq/Brazil)

向作者/读者索取更多资源

A single-phase ac-dc-ac topology to improve power quality is proposed in this study. This configuration is obtained from the addition of a floating capacitor H-bridge converter on the grid side of the conventional ac-dc-ac three-leg topology. The role of the structure is not only to ensure regulated load voltage with fixed amplitude and frequency, grid current with low harmonic content and unitary power factor, but also to mitigate fundamental overvoltage and voltage harmonics at the grid. As a consequence, the proposed topology is suitable to operate as unified power quality compensator or uninterrupted power supply. It does not use isolation transformer and is capable of generating multilevel input voltages due to the cascaded H-bridge. The operation with asymmetrical dc-link voltages is considered to increase the number of voltage levels and reduce the harmonic content of the generated input voltages. Two pulse-width modulation techniques and a control system are developed to regulate the dc-link voltages and to decrease the harmonic distortion (HD), lowering the switching stress and also the power losses. The proposed configuration is compared with the conventional one with respect to HD and semiconductor losses. Simulated and experimental results are presented for validation purposes.

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