期刊
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
卷 25, 期 6, 页码 1978-1982出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TVLSI.2017.2655079
关键词
Circuit reliability; double-node upset (DNU); radiation hardening; single-node upset (SNU); soft error
资金
- Anhui University Doctor Startup Fund [J01003217]
- National Natural Science Foundation of China [61604001, 61574052, 61371025, 61274036]
This brief presents a double-node-upset-resilient latch (DNURL) design in 22-nm CMOS technology. The latch comprises three interlocked single-node-upset-resilient cells and each of the cells mainly consists of three mutually feeding back Muller C-elements. Simulation results demonstrate the double-node upset resilience and a 73.0% delay-power-area product saving on average compared with the up-to-date DNURL designs.
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