期刊
IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES
卷 65, 期 12, 页码 5411-5421出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TMTT.2017.2771457
关键词
Digital power amplifier; digital transmitter; 5G; RF-DAC; 64-QAM; SOI CMOS
An ultra-broadband I/Q RF-DAC digital wireless transmitter architecture is proposed for 5G terminals and base stations. Broadband 1-32-GHz and tuned 20-32-GHz 2x6-bit versions of the transmitter were designed and manufactured in a production 45-nm SOI CMOS technology. They feature a process-and-temperature invariant quadrature phase generator with less than 1.4 degrees phase error from 1 to 32 GHz, and a series-stacked, gate-segmented 2x6-bit I/Q RF-DAC. The transistor-level schematics of each block, and novel series-differential inductors for broadb and common-mode rejection and differential-mode bandwidth extension are described in detail. The tuned transmitter prototype with transformer-coupled output stage achieved 19.9-dBm output power with record data rates of up to 30 Gbit/s and 24.6-pJ/bit efficiency in the 20-32-GHz range using QPSK, 16-QAM, 32-QAM, and 64-QAM modulation formats. The measured output power of the broadband transmitter is 18.4 dBm and remains larger than 13 dBm from 1 to 32 GHz. On-die generation of 16-QAM, 32-QAM, and 64-QAM modulated carriers at data rates of up to 20, 15, and 6 Gbit/s, respectively, was demonstrated.
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