期刊
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
卷 64, 期 9, 页码 2556-2568出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCSI.2017.2706722
关键词
Field programmable gate array (FPGA); processor; real-time; multi-input multi-output (MIMO); orthogonal frequency-division multiplexing (OFDM); sphere decoder; 802.11n
资金
- EPSRC [EP/H051155/1] Funding Source: UKRI
Sphere decoders allow receivers in multiple-input multiple-output (MIMO) communications systems to detect QAM symbols with quasi-optimal accuracy and low complexity compared with the ideal maximum likelihood detector. However, their high complexity relative to simple linear detectors means that the latter are still usually adopted, despite their lower detection performance. Configurable sphere decoders, such as selective spanning fast enumeration (SSFE), allow complexity to be reduced at the cost of lower performance and are hence ideal for transceivers for Internet-of-Things equipment, where scale, operating context and resource, and energy budgets vary dramatically. However, SSFE still suffers performance limitations due to the internal heuristics employed for symbol selection and enumeration and real time, and software-defined realizations for even moderately demanding MIMO standards, such as 802.11n, have not been recorded. This paper presents a new variant of SSFE which, by employing novel fast symbol enumeration and modulation dictionary spanning heuristics, increases performance and computational efficiency to the point where very substantial reductions in resource can be achieved without impacting detection accuracy relative to SSFE. This is demonstrated via a series of field programmable gate array-based detectors 2 x 2 and 4 x 4, 16-QAM 802.11n MIMO.
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