期刊
IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY
卷 27, 期 4, 页码 -出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TASC.2016.2646929
关键词
Cryogenic memory; nanodevice; single-flux-quantum logic; superconducting integrated circuit
资金
- JST ALCA
- JSPS KAKENHI [26226019, 16H02796]
- Grants-in-Aid for Scientific Research [16H02796, 26220904] Funding Source: KAKEN
We present hybridization of Josephson, CMOS, and nanocryotron (nTron) devices for a large-scale cryogenic memory application. The memory system proposed here is dynamic random access memory composed of address decoders based on an energy efficient rapid single-flux-quantum logic, nTron line drivers, a CMOS memory cell array, and Josephson current sensors. Because drivers with voltage amplification and decoders are the major causes of power dissipation in the conventional Josephson-CMOS hybrid memory, drastic reduction in power consumption is expected. We show estimates that the power consumption of a 16-Mb memory is reduced to 1.36-2.77mW, approximately 1/12 of the conventional Josephson-CMOS hybrid memory, and the access time is 0.78 ns for a read operation, when we assume a 65-nm CMOS process and a 1.0-mu m Nb/AlOx/Nb process. In the preliminary experiment, we fabricated nTrons using NbTiN thin film that are suitable for hybrid memory implementation, and measured with eight-transistor static random access memory cells fabricated using the Rohm 0.18-mu m CMOS process. We successfully triggered the nTron into the normal state, and observed output voltage of similar to 0.1 V at 13.5 K. The experimental results support the potential of the hybrid memory using NbTiN nTrons.
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