期刊
IEEE JOURNAL OF SOLID-STATE CIRCUITS
卷 52, 期 11, 页码 2934-2946出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2017.2734910
关键词
Double injection; duty-cycle corrector (DCC); injection-locked oscillator; multiplying delay-locked loop (MDLL); offset cancellation; pulsewidth comparator (PWC); spur reduction; time-to-voltage converter (TVC)
资金
- National Research Foundation of Korea (NRF) Grant through the Korean Government (MSIP) [NRF-2015R1A5A1036133]
- National Research Foundation of Korea [2015R1A5A1036133] Funding Source: Korea Institute of Science & Technology Information (KISTI), National Science & Technology Information Service (NTIS)
In this paper, we propose a low-jitter low-power digital multiplying delay-locked loop (MDLL) with a self-calibrated double reference injection scheme. To reduce jitter, the noisy edge of the oscillator is replaced by both the rising and falling edges of the clean reference, which results in 6-dB reduction in phase noise compared with a conventional single-edge injection MDLL. Reference spur caused by a frequency error of the oscillator, duty-cycle error of the reference, and circuit imperfection, such as offset and mismatch, is removed by employing three background feedback loops with a shared analog pulsewidth comparator. Implemented in 28-nm CMOS, the proposed digital MDLL generates 2.4-GHz clock and achieves a spur of -51.4 dBc and an rms jitter of 699 fs(rms) while consuming 1.5 mW from 1-V supply.
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