期刊
IEEE JOURNAL OF SOLID-STATE CIRCUITS
卷 52, 期 7, 页码 1863-1875出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2017.2690859
关键词
Adaptive clock; energy-efficient processor; fine-grained adaptive voltage scaling (AVS); integrated voltage regulator; power management unit (PMU); RISC-V; voltage dithering
资金
- Berkeley Wireless Research Center
- ASPIRE Lab
This paper presents a RISC-V system-on-chip (SoC) with integrated voltage regulation, adaptive clocking, and power management implemented in a 28 nm fully depleted silicon-on-insulator process. A fully integrated simultaneous-switching switched-capacitor DC-DC converter supplies an application core using a clock from a free-running adaptive clock generator, achieving high system conversion efficiency (82%-89%) and energy efficiency (41.8 double-precision GFLOPS/W) while delivering up to 231 mW of power. A second core serves as an integrated power-management unit that can measure system state and actuate changes to core voltage and frequency, allowing the implementation of a wide variety of power-management algorithms that can respond at submicrosecond timescales while adding just 2.0% area overhead. A voltage dithering program allows operation across a wide continuous voltage range (0.45 V-1 V), while an adaptive voltage-scaling algorithm reduces the energy consumption of a synthetic benchmark by 39.8% with negligible performance penalty, demonstrating practical microsecond-scale power management for mobile SoCs.
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