3.8 Proceedings Paper

Improvement in Electrical Properties of Al/La2O3/ZrO2/ gate stack deposited on LaON Passivated GaAs Substrate

出版社

IEEE

关键词

LaON interfacial layer; bilayer high-k; PEALD; interface trap density (Dit); CET

资金

  1. Council for Scientific, Industrial Research (CSIR), New Delhi under SAP-DRS [22(0716)/16/EMRII/2016, 503/4/DRS-III/2016-(SAP-I)]
  2. UGC under SAP-DRS [503/4/DRS-III/2016-(SAP-I)]

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The PEALD deposited La2O3/ZrO2 bilayer high-k on with and without LaON passivated GaAs substrates were investigated. The structural and electrical properties of bilayered MOS capacitors were studied in detailed. The dielectric constant (k) of = 20.75, effective oxide charge (Q(eff)) of 1.094 x 10(12)cm(-2), interface trapped density (D-it) 1.655 x 10(12) eV(-1)cm(-2) and leakage current density (J = 8.93 x10(-5) at 1V) were obtained for the LaON passivated GaAs MOS capacitor. The lowest capacitance equivalent thickness (CET) of 0.649 nm extracted from C-V curve for LaON passivated GaAs sample. The presence of LaON passivation layer in MOS device effectively blocks the formation of As-oxides and Ga-oxides at interface, which significantly improves the interfacial and electrical properties of the device and can be the effective passivation for the futuristic high mobility substrate devices

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