Improving Voltage Sensor Noise Immunity in a High Voltage and High dv/dt Environment

This work focuses on improving voltage sensor noise immunity in a high voltage and high dv/dt environment. This is demonstrated in a 10 kV SiC MOSFET based Modular Multilevel Converter phase leg. The design is improved through several iterations while employing methodologies such as shielding, PCB layout techniques, improving the signal-to-noise ratio, and reducing the bandwidth of the sensor to reduce the noise impact of the high dv/dt of the SiC device. The impact of each methodology on the design is stressed, and the final version of the sensor shows significant improvement in noise immunity while offering the best high voltage design available.