PRESENT Hardware Implementation for Concurrent Fault Detection Architecture

Efficient fault tolerant implementation of lightweight cryptography hardware is a main challenge of secure hardware in IoT, RFID and sensor network. In this paper, we propose low cost PRESENT architecture using 80-bit key and 64-bit input data with fault detection capability. Our proposed architecture utilizes different S-Boxes implementations in which both encryption and decryption processes are integrated in one data path. The simulation results of our fault detection structure are compared with previous related works. The results are compared in terms of area, throughput and efficiency. This comparison illustrate that our fault detection architecture outperforms related works in the comparison metrics.