3.8 Proceedings Paper

Monolithic 3D Integration of High Endurance Multi-Bit Ferroelectric FET for Accelerating Compute-In-Memory

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IEEE
DOI: 10.1109/IEDM13553.2020.9371974

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  1. ASCENT, one of six centres in JUMP - DARPA
  2. Semiconductor Research Corporation (SRC)
  3. IMPACT center in nCORE - SRC

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We demonstrate, for the first time, monolithic 3D (M3D) integration of back-end-of-line (BEOL) compatible Hf0.5Zr0.5O2 (HZO) ferroelectric FET (FeFET) with front-end-of-line (FEOL) high-k/metal gate (HKMG) Si-NMOS. We use low thermal budget (<400 degrees C) processing to integrate HZO with 1% Tungsten (W)-doped amorphous In2O3 (IWO) semiconducting oxide channel and demonstrate high remnant polarization charge density 2P(R), of 40 mu C/cm(2) with reliable switching characteristics. We report (a) read memory window of 0.45V in ultra-scaled 20nm channel length IWO FeFET, (b) write speed of 100ns, and (c) write endurance >10(8) cycle. We further demonstrate a 2bit/cell synaptic weight cell with well separated conductance states. System-level analysis of compute-in-memory (CIM) accelerators for performing inference on CIFAR-10 image dataset using VGG-8 model shows that 22nm BEOL FeFET achieves 3x higher energy-efficiency than 7nm SRAM while occupying a smaller memory array area due to area folding enabled by M3D architecture.

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