期刊
2020 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)
卷 -, 期 -, 页码 -出版社
IEEE
DOI: 10.1109/IEDM13553.2020.9371926
关键词
-
资金
- EC under the Graphene flagship [CNECT-ICT-604391]
Double gated WS2 transistors with gate length down to 18 nm are fabricated in a 300mm Si CMOS fab. By using large statistical data sets and mapping uniformity on full 300mm wafer, we built an integration vehicle where impact of each process step can be understood and developed accordingly to enhance device performance. In-depth analysis of V-T variability reveals multiple possible sources at different length scales, with the most prominent one being the channel material. The work presented here paves the way towards industrial adoption of 2D materials.
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