期刊
IEEE SOLID-STATE CIRCUITS LETTERS
卷 3, 期 -, 页码 446-449出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LSSC.2020.3025667
关键词
Contention free; effective clock loading; redundant clock; redundant transistor; static
A redundancy eliminated flip-flop (REFF) is presented in 28-nm LP process, targeting wide-range voltage scalability (1-0.3 V). The REFF removes redundant clock transitions to reduce dynamic power consumption and further eliminates redundant transistors with topological and logical methods while keeping it fully static and contention free. The measured power is reduced by 70%/59% with 0%/10% activity at 1-V compared to the TGFF, and 100 dies from five corners were functional down to 0.28 V.
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