期刊
IEEE SOLID-STATE CIRCUITS LETTERS
卷 3, 期 -, 页码 158-161出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LSSC.2020.3008298
关键词
Digital phase-locked loop (DPLL); low jitter; low power; reference sampling DPLL (RS-DPLL); SAR ADC
资金
- Science Foundation Ireland [14/RP/I2921]
- Marie Sklodowska-Curie Actions [746142]
- Marie Curie Actions (MSCA) [746142] Funding Source: Marie Curie Actions (MSCA)
This letter proposes a low-power reference-sampling digital phase-locked loop (RS-DPLL). Without any need for a power-hungry low-noise buffer, a reference waveform is directly sampled by a reference-sampling phase detector exploiting a bottom-plate sampling technique. The sampled voltage error is digitized through a gated amplifier incorporated with an 8-bit SAR-ADC of tiny size resulting in high effective resolution while consuming <0.2 mW. The proposed RS-DPLL is implemented in 28-nm CMOS. Despite the limited slew-rate of the input reference waveform, the proposed architecture achieves 355-fs rms jitter and consumes only 1.1 mW. This leads to the integrated phase noise FoM of -249 dB.
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