FPGA-based architecture for bi-cubic interpolation: the best trade-off between precision and hardware resource consumption

An accurate and low-cost design of the image interpolation unit is a crucial part for many real-time image processing systems. To reach this goal, bi-cubic interpolation is generally selected because it provides the best trade-off between computational complexity and interpolation quality. The aim of this paper is to study the optimal hardware implementation of heterogeneous bi-cubic interpolation. Bi-cubic algorithm is reformulated and improved for FPGA implementation. This improved algorithm avoids twelve redundant calculations and reduces the number of multipliers by 25%. Hardware precision versus resource utilization is studied to minimize the quantization error of hardware realization, and to obtain the best trade-off between design cost and accuracy. A compromise that reduces 33,33% of bit-width utilization with a precision higher than 99.922% is reached. Besides, the proposed architecture is fully pipelined to reach high operating frequency. Instantiation on Xilinx and Intel targets shows the benefit of our approach, especially in terms of hardware resource consumption.

Automated summary

This paper studies the optimal hardware implementation of heterogeneous bi-cubic interpolation, improving the algorithm to reduce computational complexity and hardware resource consumption, achieving a compromise in bit-width utilization.