期刊
IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING
卷 9, 期 2, 页码 651-663出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TETC.2019.2953139
关键词
Error correction codes; Block codes; Tools; Decoding; Parity check codes; Error correction; Integrated circuit reliability; Error correction codes; memories; soft errors
资金
- Fundamental Research Funds for the Central Universities [HIT.KISTP.201404]
- Harbin science and innovation research special fund [2015RAXXJ003]
- Special found for development of Shenzhen strategic emerging industries [JCYJ20150625142543456]
- Madrid Community research project TAPIR-CM [P2018/TCS-4496]
- TEXEO project - Spanish Ministry of Economy and Competitivity [TEC2016-80339-R]
As technology evolves, radiation-induced soft errors in memories become more complex, requiring new error correction codes development. Memory layout and data types have different impacts on error patterns, necessitating the design of custom error correction codes for specific needs.
As technology scales, radiation induced soft errors create more complex error patterns in memories with a single particle corrupting several bits. This poses a challenge to the Error Correction Codes (ECCs) traditionally used to protect memories that can correct only single bit errors. During the last decade, a number of codes have been developed to correct the emerging error patterns, focusing initially on double adjacent errors and later on three bit burst errors. However, as the memory cells get smaller and smaller, the error patterns created by radiation will continue to change and thus new codes will be needed. In addition, the memory layout and the technology used may also make some patterns more likely than others. For example, in some memories, there maybe elements that separate blocks of bits in a word, making errors that affect two blocks less likely. Finally, for a given memory, depending on the data stored, some error patterns may be more critical than others. For example, if numbers are stored in the memory, in most cases, errors on the more significant bits have a larger impact. Therefore, for a given memory and application, to achieve optimal protection, we would like to have a code that corrects a given set of patterns. This is not possible today as there is a limited number of code choices available in terms of correctable error patterns and word lengths. However, most of the codes used to protect memories are linear block codes that have a regular structure and which design can be automated. In this paper, we propose the automation of error correction code design for memory protection. To that end, we introduce a software tool that given a word length and the error patterns that need to be corrected, produces a linear block code described by its parity check matrix and also the bit placement. The benefits of this automated design approach are illustrated with several case studies. Finally, the tool is made available so that designers can easily produce custom error correction codes for their specific needs.
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