A Fully Digital True Random Number Generator With Entropy Source Based in Frequency Collapse

All cryptography systems have a True Random Number Generator (TRNG). In the process of validating, these systems are necessary for prototyping in Field Programmable Gate Array (FPGA). However, TRNG uses an entropy source based on non-deterministic effects challenging to replicate in FPGA. This work shows the problems and solutions to implement an entropy source based on frequency collapse in multimodal Ring Oscillators (RO). The entropy source implemented in FPGA pass all SP800-90B tests from the National Institute of Standards and Technology (NIST) with a good entropy compared to related works. The TRNG passes all NIST SP800-22 with and without the post-processing stage. Besides, the TRNG and the post-processing stage pass all tests of Application notes and Interpretation of the Scheme (AIS31). The TRNG implementation on a Xilinx Artix-7 XC7A100TCSG324 FPGA occupies less than 1% of the resources. This work presents 0.62 mu s up to 9.92 mu s of sampling latency and 1.1 Mbps up to 9.1 Mbps of bit rate throughput.

Automated summary

This work addresses the implementation of an entropy source based on frequency collapse in Ring Oscillators in FPGA, passing NIST tests with good entropy. The TRNG implementation occupies less than 1% of FPGA resources and demonstrates moderate sampling latency and bit rate throughput.