相关参考文献
注意：仅列出部分参考文献，下载原文获取全部文献信息。On the Trap Locations in Bulk FinFETs After Hot Carrier Degradation (HCD)
Zhuoqing Yu et al.
IEEE TRANSACTIONS ON ELECTRON DEVICES (2020)
A physics-aware compact modeling framework for transistor aging in the entire bias space
Zhicheng Wu et al.
2019 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) (2019)
Method to estimate profile of threshold voltage degradation in MOSFETs due to electrical stress
Yeohyeok Yun et al.
MICROELECTRONICS RELIABILITY (2018)
Characterization and modeling of electrical stress degradation in STI-based integrated power devices
Susanna Reggiani et al.
SOLID-STATE ELECTRONICS (2014)
Numerical analysis of localised charges impact on static and dynamic performance of nanoscale cylindrical surrounding gate MOSFET based CMOS inverter
Rajni Gautam et al.
MICROELECTRONICS RELIABILITY (2013)
Effect of localised charges on nanoscale cylindrical surrounding gate MOSFET: Analog performance and linearity analysis
Rajni Gautam et al.
MICROELECTRONICS RELIABILITY (2012)
Refinement of the subthreshold slope modeling for advanced bulk CMOS devices
Arnaud Pouydebasque et al.
IEEE TRANSACTIONS ON ELECTRON DEVICES (2007)
分享论文
