期刊
2021 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS)
卷 -, 期 -, 页码 -出版社
IEEE
DOI: 10.1109/IRPS46558.2021.9405106
关键词
Charge trapping; hot carrier; compact model; transistor aging
An analytical device aging modelling framework is demonstrated, covering microscopic degradation physics to aged I-V characteristics. Through expanded reliability oriented I-V compact model, proposed analytical solution for channel carrier profiling, and conversion through Poisson's equation, local degradation is propagated into aged I-V characteristics, validated across a wide range of stress conditions in scaled finFET technology.
An analytical device aging modelling framework, ranging from microscopic degradation physics up to the aged I-V characteristics, is demonstrated. We first expand our reliability oriented I-V compact model, now including temperature and body-bias effects; second, we propose an analytical solution for channel carrier profiling which-compared to our previous work-circumvents the need of TCAD aid; third, through Poisson's equation, we convert the extracted carrier density profile into channel lateral and oxide electric fields; fourth, we represent the device as an equivalent ballistic MOSFETs chain to enable channel slicing and propagate local degradation into the aged I-V characteristics, without requiring computationally-intensive self-consistent calculations. The local degradation in each channel slice is calculated with physics-based reliability models (2-state NIWP, SVE/MVE). The demonstrated aging modelling framework is verified against TCAD and validated across a broad range of V-G/V-D/T stress conditions in a scaled finFET technology.
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