A 336 Gbit/s Full-Parallel Window Decoder for Spatially Coupled LDPC Codes

Low-Density Parity-Check (LDPC) codes are among the most powerful Forward Error Correction (FEC) schemes and part of many communication standards. Emerging use cases are expected to require data rates towards Tbit/s, which is one to two orders of magnitude higher than the throughput specified in 5G-NR. For throughputs towards Tbit/s, state-of-the-art LDPC soft decoders are restricted to short code block sizes of several hundreds to thousands of bits due to routing congestion challenges, forcing a firm limit to the overall communications performance of the transmission system. In this paper, we focus on a relatively new class of LDPC codes, denoted as Spatially Coupled LDPC (SC-LDPC) codes. For the first time, we show that these codes enable efficient, very high throughput (>> 100 Gbit/s) decoding of large code block sizes. To this end, we present an SC-LDPC decoder for a length N = 51328 terminated SC-LDPC code with sub-block size c = 640 and coupling width m(s) = 1, that achieves a throughput of 336 Gbit/s in a 22nm FD-SOI technology, which is about 50 times higher than the fastest SC-LDPC decoder in literature. In contrast to existing work, the presented decoder is based on the Full-Parallel Window Decoder (FPWD) architecture. We propose algorithmic and architectural modifications to shorten the critical path and to reduce the routing complexity of the FPWD resulting in higher throughput as well as better energy and area efficiency for the modified decoder. The decoder furthermore outperforms a state-of-the-art reference architecture that was implemented for the same code in the same technology in terms of throughput and latency.

Automated summary

LDPC codes are powerful FEC schemes capable of high throughput decoding, while SC-LDPC codes enable efficient decoding of large code blocks with even higher efficiency.