期刊
IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY
卷 9, 期 -, 页码 868-875出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JEDS.2021.3114648
关键词
3D integration; Cu bonding; wafer-level bonding; flip-chip bonding; Au passivation
资金
- Center for the Semiconductor Technology Research from the Featured Areas Research Center Program
- Ministry of Science and Technology, Taiwan [MOST 110-2634-F-009-027, MOST 109-2221-E-009-023-MY3, MOST 110-2221-E-A49-086-MY3]
Fine pitch Cu/SiO2 hybrid bonding was successfully achieved at a low temperature of 120 degrees C using Au passivation method, showing stable electrical performance. This method exhibits excellent bonding quality, low thermal budget, and high reliability, making it highly feasible for 3D IC and heterogenous integration applications.
Fine pitch Cu/SiO2 hybrid bonding has been successfully demonstrated at a low temperature of 120 degrees C, a breakthrough, using Au passivation method in this work. To explore the bonding mechanism of passivation structures for hybrid bonding in details, Cu-Cu direct bonding with Au passivation on both wafer-level and chip-level has been discussed, including analyses of AFM, SAT, TEM, electrical measurements, and reliability test. Cu/SiO2 hybrid bonding with the fine pitch structure with stable electrical performance can be achieved at low bonding temperature under an atmospheric environment. Accordingly, this Au passivation scheme for Cu/SiO2 hybrid bonding with excellent bonding quality, low thermal budget, and high reliability shows a great feasibility for the 3D IC and heterogenous integration applications.
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