Electrical design challenges in High Bandwidth Memory and Advanced Interface Bus interfaces on HD-FOWLP technology

Wide and slow bus interfaces such as High Bandwidth Memory (ABM) and Advanced Interface Bus (MB) are the main drivers behind the development and implementation of technologies such as Embedded Multi-die Interconnect Bridge (EMIB) and Chip-on-Wafer-on-Substrate (CoWoS). These technologies can create very dense interconnect structures using back end of line (BEOL) approaches used to interconnect chiplets and to form functional system in package applications. With recent improvements in fabrication and process technologies organic based high density redistribution layer approaches such HD-FOWLP have become popular alternatives to EMIB and CoWoS. Redistribution layers with 2um x 2um cross section and 2um space between adjacent lines or lum x lum cross section with a minimum spacing of lum have become achievable with the current fabrication technology. In this work the electrical design challenges in organic based fine RDL packages have been studied via simulation and electrical measurements.

Automated summary

This study discussed the electrical design challenges in organic-based fine RDL packages using simulations and electrical measurements. Advanced technologies such as EMIB, CoWoS, and HD-FOWLP are driving the development and implementation of interconnect technologies.