期刊
IEEE ACCESS
卷 9, 期 -, 页码 141321-141328出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/ACCESS.2021.3119858
关键词
MOSFET; Logic gates; Semiconductor process modeling; Threshold voltage; TFETs; Semiconductor device modeling; Silicon; Drain induced barrier enhancement (DIBE); drain induced barrier lowering (DIBL); gate-on-drain overlap; leakage current; MOSFET; scaling; short channel effects (SCE); subthreshold swing; and threshold voltage
This paper presents a detailed study on the effect of drain induced barrier enhancement (DIBE) on the subthreshold swing and OFF-state current of a short channel MOSFET using calibrated 2-D simulations. The study demonstrates that gate-on-drain overlap in a short channel MOSFET leads to DIBE, resulting in near ideal subthreshold swing, reduced DIBL, constant threshold voltage, and improved ION/IOFF ratio at room temperature.
In this paper, with the help of calibrated 2-D simulations, we report a detailed study on the effect of drain induced barrier enhancement on the subthreshold swing and OFF-state current of a short channel MOSFET. We demonstrate that the presence of gate-on-drain overlap in a short channel MOSFET leads to drain induced barrier enhancement (DIBE). We show that as a result of DIBE, a MOSFET can achieve near ideal subthreshold swing, diminished DIBL, constant threshold voltage and improved ION/IOFF ratio at room temperature, without being affected by channel length variations.
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