HARDWARE IMPLEMENTATION OF ITERATIVE PROJECTION-AGGREGATION DECODING OF REED-MULLER CODES

In this work, we present a simplification and a corresponding hardware architecture for hard-decision recursive projection-aggregation (RPA) decoding of Reed-Muller (RM) codes. In particular, we transform the recursive structure of RPA decoding into a simpler and iterative structure with minimal error-correction degradation. Our simulation results for RM(7; 3) show that the proposed simplification has a small error-correcting performance degradation (0:005 in terms of channel crossover probability) while reducing the average number of computations by up to 40%. In addition, we describe the first fully parallel hardware architecture for simplified RPA decoding. We present FPGA implementation results for an RM(6; 3) code on a Xilinx Virtex-7 FPGA showing that our proposed architecture achieves a throughput of 171 Mbps at a frequency of 80 MHz.

Automated summary

This work presents a simplification and corresponding hardware architecture for hard-decision recursive projection-aggregation decoding of Reed-Muller codes, achieving minimal error-correction degradation while reducing average computations. The proposed fully parallel hardware architecture for simplified RPA decoding shows promising FPGA implementation results for RM codes on Xilinx Virtex-7 FPGA, achieving high throughput at a frequency of 80 MHz.