3.8 Article

Hardware Acceleration of Large-Scale CMOS Invertible Logic Based on Sparse Hamiltonian Matrices

相关参考文献

注意:仅列出部分参考文献,下载原文获取全部文献信息。
Article Computer Science, Hardware & Architecture

A Design Framework for Invertible Logic

Naoya Onizawa et al.

Summary: In this article, a design framework for invertible logic circuits is introduced, employing linear programming to create a Hamiltonian library and achieving faster simulation and verification compared to traditional methods. Several invertible-logic circuits were designed and emulated in SystemC, showing a significant improvement in simulation speed.

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS (2021)

Article Multidisciplinary Sciences

A stochastic quantum program synthesis framework based on Bayesian optimization

Yao Xiao et al.

Summary: BayeSyn, utilizing enhanced stochastic program synthesis and Bayesian optimization, can automatically generate quantum programs with lower cost in high-dimensional program space. Bayesian optimization plays a significant role in fine-tuning hyperparameters to generate suitable quantum programs.

SCIENTIFIC REPORTS (2021)

Article Computer Science, Information Systems

Sparse Random Signals for Fast Convergence on Invertible Logic

Naoya Onizawa et al.

Summary: This paper introduces the use of sparse random signals for fast convergence in invertible logic. By replacing a part of the typical dense random signals with zero values, sparse random signals can induce a relatively relaxed transition in the spin network and reach the global minimum energy more quickly.

IEEE ACCESS (2021)

Article Engineering, Electrical & Electronic

In-Hardware Training Chip Based on CMOS Invertible Logic for Machine Learning

Naoya Onizawa et al.

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS (2020)

Article Computer Science, Information Systems

Training Hardware for Binarized Convolutional Neural Network Based on CMOS Invertible Logic

Duckgyu Shin et al.

IEEE ACCESS (2020)

Article Engineering, Electrical & Electronic

Efficient CMOS Invertible Logic Using Stochastic Computing

Sean C. Smithson et al.

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS (2019)

Article Computer Science, Artificial Intelligence

Weighted p-Bits for FPGA Implementation of Probabilistic Circuits

Ahmed Zeeshan Pervaiz et al.

IEEE TRANSACTIONS ON NEURAL NETWORKS AND LEARNING SYSTEMS (2019)

Article Computer Science, Artificial Intelligence

A Survey of ReRAM-Based Architectures for Processing-In-Memory and Neural Networks

Sparsh Mittal

MACHINE LEARNING AND KNOWLEDGE EXTRACTION (2019)

Article Computer Science, Hardware & Architecture

Gradient Descent Using Stochastic Circuits for Efficient Training of Learning Machines

Siting Liu et al.

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS (2018)

Article Computer Science, Hardware & Architecture

VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing

Arash Ardakani et al.

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS (2017)

Article Computer Science, Hardware & Architecture

Area/Energy-Efficient Gammatone Filters Based on Stochastic Computation

Naoya Onizawa et al.

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS (2017)

Article Mathematics, Applied

Further scramblings of Marsaglia's xorshift generators

Sebastiano Vigna

JOURNAL OF COMPUTATIONAL AND APPLIED MATHEMATICS (2017)

Article Engineering, Electrical & Electronic

Architectures for Recursive Digital Filters Using Stochastic Computing

Yin Liu et al.

IEEE TRANSACTIONS ON SIGNAL PROCESSING (2016)

Article Engineering, Electrical & Electronic

Gabor Filter Based on Stochastic Computation

Naoya Onizawa et al.

IEEE SIGNAL PROCESSING LETTERS (2015)

Article Computer Science, Hardware & Architecture

Computation on Stochastic Bit Streams Digital Image Processing Case Studies

Peng Li et al.

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS (2014)

Article Physics, Multidisciplinary

Ground-state spin logic

J. D. Whitfield et al.

Proceedings Paper Computer Science, Hardware & Architecture

Towards a Universal FPGA Matrix-Vector Multiplication Architecture

Srinidhi Kestur et al.

2012 IEEE 20TH ANNUAL INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES (FCCM) (2012)

Article Engineering, Electrical & Electronic

Fully Parallel Stochastic LDPC Decoders

Saeed Sharifi Tehrani et al.

IEEE TRANSACTIONS ON SIGNAL PROCESSING (2008)

Article Telecommunications

Stochastic decoding of LDPC codes

Saeed Sharifi Tehrani et al.

IEEE COMMUNICATIONS LETTERS (2006)

Article Engineering, Electrical & Electronic

Iterative decoding using stochastic computation

VC Gaudet et al.

ELECTRONICS LETTERS (2003)

Article Computer Science, Hardware & Architecture

Stochastic neural computation I: Computational elements

BD Brown et al.

IEEE TRANSACTIONS ON COMPUTERS (2001)