Hardware Acceleration of Large-Scale CMOS Invertible Logic Based on Sparse Hamiltonian Matrices

Invertible logic has been recently presented that can realize bidirectional computing based on Hamiltonians for solving several critical issues, such as integer factorization and training neural networks. However, a hardware architecture for supporting large-scale general-purpose invertible logic has not been studied. In this paper, we introduce a scalable hardware architecture based on sparse Hamiltonian matrices. In order to store and compute the Hamiltonians efficiently in hardware, a sparse matrix representation of PTELL (partitioned and transposed ELLPACK) is proposed. A memory size of PTELL can be smaller than that of a conventional ELL by reducing the number of paddings while parallel reading of non-zero values are realized for high-throughput operations. As a result, PTELL achieves around 1% and 10% memory usages of a conventional dense and ELL matrices, respectively, in case of invertible multipliers. In addition, the proposed hardware accelerator of invertible logic for supporting arbitrary Hamiltonians is implemented on Xilinx VU9P FPGA, which achieves around two orders of magnitude faster than a 16-core Intel Xeon implementation.

Automated summary

The paper introduces a scalable hardware architecture based on sparse Hamiltonian matrices and proposes a sparse matrix representation of PTELL for efficiently storing and computing Hamiltonians in hardware, achieving high-throughput operations with reduced memory usage.