Network-on-Interposer Design for Agile Neural-Network Processor Chip Customization

Chiplet based multi-die integration has been thought as a key enabler of the agile chip development flow. For 2.5D based multi-die system, Network on Interposer plays an essential role in the performance and the development cost of the chips. This work proposed a reusable NoI design for agile AI chip customization. The proposed NoI design can self-adapt to the inter-die communication patterns of various neural network applications, so the produced interposers can be reused across different AI chip specifications. Experimental results show the proposed NoI design brings 42.7%similar to 79.5% of total data communication latency reduction in different scenarios, and it also decreased the area overhead by 26.4%.

Automated summary

The reusable Network on Interposer design proposed in this study enables adaptive communication patterns for various AI chip specifications, leading to significant reductions in data communication latency and area overhead.