期刊
2021 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)
卷 -, 期 -, 页码 -出版社
IEEE
DOI: 10.1109/IEDM19574.2021.9720506
关键词
-
资金
- imec's Industrial Affiliation Program for storage memories
A physical modeling approach is presented to explain the non-ideal ISPP slope in charge trap layer (CTL) flash memory and its impact on 3-D NAND vertical pitch scaling. An expression for the V-T change rate is derived to reproduce experimental vertical NAND ISPP slopes, and a 2.5-D TCAD model is implemented to show significant program voltage increase in realistic 3-D NAND flash devices with scaling vertical pitch. Mitigation measures such as high-k CTL and airgaps are evaluated for scaled pitch.
We present a physical modeling approach that explains the non-ideal ISPP slope in charge trap layer (CTL) flash memory and its impact on 3-D NAND vertical pitch scaling. First, we derive an expression for the V-T change rate and use its field dependence to reproduce experimental vertical NAND ISPP slopes. Next, we implement a 2.5-D TCAD model based on these insights and show significant program voltage increase (>5V) in realistic 3-D NAND flash devices with scaling vertical pitch (down to lOnm). Finally, we evaluate high-k CTL and airgaps as mitigation measures at scaled pitch.
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